Many Very Large Scale Integration (VLSI) silicon chips employ the so-called Level Sensitive Scan Design (LSSD) methodology in order to attain high test coverage for the logic circuits built in the IC chips. This design methodology permits chip latches to be used effectively as pseudo-I/O's, allowing an easier stimulation and readout of internal nets (or nodes). Since an output of each latch is connected to an input of the next, all the latches within the IC may be configured into one or more shift registers. Each register will, hereinafter, be referred to as a LSSD "scan chain" or "scan string".
A significant drawback of LSSD resides in the fact that shift registers occupy a substantial amount of real estate. To date, an advanced silicon chip may include as many as 50,000 latches typically divided in about 50 shift register. Admittedly, it would be too time consuming to exhaustively test all the scan chains in the IC chip.
During chip test, the correct operation of the shift register is verified by two tests know as Flush and Scan tests. In the first case, the registers are set in a Flush mode, i.e., the scan clocks are held active, so that they behave as logical delay lines. During the Scan test, two scan clock signals are pulsed without overlapping in order to verify that the register has the correct number of latches.
FIG. 1a illustrates the operation of a conventional five-latch LSSD shift register. The Scan-In signal SI remains at a low level except during the third couple of scan clock signals. During this cycle, the A clock signal loads the scan-in data in the master latch of the master/slave latch configuration, then the B clock signal transfers this data from the master to the slave latch thereof. Since the output of the slave latch is connected to the input of the next latch, data will be loaded in latch 2 during cycle number 4. During this cycle 4, the Scan-In signal SI, which reverted back to a low, causes latch 1 to be loaded with a "0". When the B clock in cycle 7 switches to a high, the "1" that was loaded in latch 1 during cycle 3 appears on the Scan-Out signal SO. One cycle later, this SO reverts back to "0" and the data is entered during cycle 4.
FIG. 1b illustrates the case of a non-LSSD shift register. The only difference resides in the use of a single clock signal to exercise the register instead of two. As apparent from FIGS. 1a-1b, the Scan Out signal SO is the same in both cases.
Although these tests are simple and may be applied very quickly, they are capable of only testing up to 30% of the logic. In reality, the chip fallout from Flush and Scan tests is often as high as 50% of the total chip fallout. This is due to a high probability of scan chain failure in the presence of two or more random defects, so that a larger percentage of defective chips will fail at least one of these tests.
Although shift registers are formed from rather simple circuits, it is never easy to diagnose any given fault, especially when the malfunction is due to an open circuit. This failure can be attributed to either the latch itself, to the connection between two latches or, frequently, to the connecting wires that feed the clock signals to the latch. To encompass all these potential sources of failures, one should normally consider a failing cell in the shift register rather than a failing latch which is somewhat more limitative. However, it will be referred to, henceforth, for sake of simplicity, as a failing latch.
The method described in U.S. Pat. No. 4,630,270, of common assignee, has been extensively used in the art. The method described allows diagnosing a failing latch in a shift register by observing the Idd current which exhibits transient spikes generated by each latch switching when the shift register is set in a Flush mode, and when a square wave is applied to its scan input pad. The method is based upon discovery that Idd current variations stop, i.e., the Idd current remains at a constant value when the incoming data arrives at the failing latch. By displaying Idd current variations on an oscilloscope, the rank of the faulty latch can be accurately determined, since it is possible to identify some of the latches forming the register. However, with recent improvements in the semiconductor manufacturing technology, ICs are becoming faster, leading to smaller Idd spikes, both in amplitude and duration, making it more difficult to estimate the rank of the faulty latch with any degree of accuracy. Recently, with the introduction of 0.5 .mu. lithography, the precision of the diagnostic made by this method is substantially degraded (the faulty latch can only be identified as belonging to a group of 10 to 20 latches), so that this method results in a very imprecise and thus unacceptable diagnostic. As a direct consequence, failure analysis becomes significantly more difficult because more nets must be visually examined for each defective shift register. Moreover, for each latch of the group mentioned above, output nets linking a latch as well as the clock nets feeding the latch (i.e., A, B and possibly C clocks in case of an LSSD latch), all require full checking. Finally, the success rate, i.e., the percentage of defects identified by failure analysis is low.
Moreover, in today's semiconductor industry, the time allotted for responding is a determining factor in any failure analysis of logic ICs. Typical turn around time (TAT) for ASIC diagnostic and physical failure analysis is mostly driven by the time required to localize the failure.